1. Field of the Invention
The invention disclosed and claimed herein generally pertains to an apparatus for monitoring at least one voltage of each domain in an electronic chip partitioned into multiple voltage domains. More particularly, the invention pertains to apparatus of the above type wherein a single conductive link, such as a single pair of C4 pins, is used to measure the voltage levels of all the voltage domains of the chip. Even more particularly, the invention pertains to apparatus of the above type wherein voltages of respective domains may be applied to the single conductive link in a prescribed sequence.
2. Description of the Related Art
It has been conventional practice to measure or monitor voltage drop of an integrated circuit (IC), or other electronic semiconductor chip, by dedicating two conductive pins of the chip for this purpose. These pins, commonly referred to as C4 pins, are conductive elements provided to attach the chip to its associated package. One of the pins is coupled to ground, and the other pin is tapped into the chip power distribution. This pin is routed from the chip through the package, to enable voltage measurement at the card level during system operation.
In recent years, it has been recognized that there are benefits in using multi-core microprocessors for certain tasks or applications. In a multi-core processor, two or more independent processors are combined in a single chip or IC. In one useful application, multi-core processors are used to enable a computing device to exhibit a form of thread-level parallelism (TLP), without including microprocessors in separate packages. However, placing multiple processors on the same chip has caused power densities to increase. Moreover, it has become necessary to partition the chip into multiple voltage domains or voltage islands, wherein each domain has a voltage that must be set to a specified point or level. This must be done to maximize yield and/or performance.
Partitioning a chip into multiple domains has required that a number of C4 pin pairs must be dedicated on the chip, one pair for monitoring the voltage of each domain, to sense each domain. Respective voltages are monitored, so that each voltage domain can be adjusted to the correct voltage set point. A currently used arrangement of this type is shown in FIG. 1, and is described hereinafter. However, requiring one pair of pins for each voltage domain is expensive. Moreover, each pair of pins used for voltage monitoring or sensing is not available for sending power to a chip, or for signaling therewith. Accordingly, the chip must be provided with additional pairs of pins for these tasks, which can further increase both cost and complexity of the chip. It would thus be beneficial to provide some means for reducing the number of pin pairs that are required for voltage monitoring.